WAIT Statements – 2 MCQ’s

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This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “WAIT Statements – 2″.

1. Given that a process has no sensitivity list and has only one WAIT statement which is WAIT FOR statement. How many signals are there to which process is sensitive?
a) 0
b) 1
c) 2
d) Can’t be determined

2. WAIT statement provides more flexibility than sensitivity list.
a) True
b) False

3. Which of the following statement uses only 1 signal?
a) WAIT FOR
b) WAIT UNTIL
c) WAIT ON
d) WAIT UNTIL and WAIT FOR

4. Which of the following WAIT statement is most useful for implementing a synchronous sequential circuit?
a) WAIT ON
b) WAIT FOR
c) WAIT UNTIL
d) WAIT TIME

5. In case of sensitivity list the process suspends at the end of the process and in WAIT statement it suspends ____________
a) At the beginning
b) At the end
c) At the beginning of architecture
d) Where the WAIT statement is encountered

6. What is the deadlock condition in VHDL?
a) When WAIT statement keeps on waiting forever
b) When WAIT UNTIL statement uses more than one signal
c) When WAIT ON statement has only one signal
d) When WAIT FOR statement doesn’t have any time clause

7. In combinational logic, how many WAIT statements can be used?
a) 0
b) 1
c) 2
d) 3

8. In a procedure is called from a process having a sensitivity list, how many wait statements one can use?
a) 3
b) 2
c) 1
d) 0

9. Refer to the code given below, which kind of circuit is implemented?

PROCESS
BEGIN
WAIT on a, b;
z <= a AND b;
END PROCESS;

a) Combinational
b) Synchronous sequential
c) Asynchronous sequential
d) State machine

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