June 12, 2021

Structural Modelling – 3 MCQ’s

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This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Structural Modelling – 3″.

1. Refer to the model given below, which circuit is designed?

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, x);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, y);
END arch1;

a) Half adder
b) Comparator 2- bits
c) Full adder
d) Can’t be determined

2. There is a special function called interconnect () to define interconnections between pins.
a) True
b) False

3. Which of the following is the correct order for a structural model in VHDL?
a) Libraries, Entity declaration, Component declaration, Component instantiation
b) Libraries, Component declaration, Entity declaration, Component instantiation
c) Libraries, Entity declaration, Component instantiation, Component declaration
d) Component declaration, Libraries, Entity declaration, Component instantiation

4. Refer to the architecture given below, there are two outputs called x and y. The structure defined is a full adder circuit. Which of the outputs corresponds to sum output of the adder?

ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, y);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, x);
END arch1;

a) y
b) x
c) s5
d) c

5. What is the correct syntax for mapping a GENERIC parameter in structural modeling?
a) label : component_name GENERIC MAP(parameter_list) PORT MAP(port_list)
b) label : component_name GENERIC MAP(parameter_list)
c) label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)
d) label : parameter_name GENERIC MAP(parameter_list) PORT MAP(port_list)

6. Which modeling style is used in code given below?

ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
Architecture arch OF design IS
BEGIN
x <= a XOR b XOR c;
y <= (a AND b) OR (b AND c) OR (a AND c);
END arch;
ARCHITECTURE arch1 OF design IS
COMPONENT comp1 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp3 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: comp1 PORT MAP(a, b, s1);
X2 : comp1 PORT MAP(s1, c, x);
X3: comp2 PORT MAP(a, b, s2);
X4 : comp2 PORT MAP(a, c, s3);
X5: comp2 PORT MAP(b, c, s4);
X6: comp3 PORT MAP(s2, s3, s5);
X7: comp3 PORT MAP(s4, s5, y);
END arch1;

a) Behavioral and structural
b) Structural
c) Dataflow
d) Dataflow and Structural

7. It is possible to use a GENERIC parameter as a separate component.
a) True
b) False

8. The structural code for 4-bit adder is given below.

COMPONENT adder IS
GENERIC (n : INTEGER := 3);
PORT(input : IN BIT_VECTOR(n DOWNTO 0);
output : OUT BIT_VECTOR(n DOWNTO 0));
END COMPONENT;

If user want to convert this in an 8 bit adder, which of the following variable should be changed?
a) n
b) input
c) output
d) component

9. A component instantiation statement generates a(n) _______ of the component.
a) Class
b) Behavior
c) Structure
d) Object

10. What is the other name for implicit mapping?
a) Nominal mapping
b) Positional mapping
c) Explicit mapping
d) Inclusive mapping

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