Structural Modelling – 2 MCQ’s

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This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Structural Modelling – 2″.

1. Which of the following function is used to map the component?
a) COMPONENT INSTANTIATE
b) PORT MAP
c) GENERIC MAP
d) USE

2. How many ways are there in VHDL to map the components?
a) 1
b) 2
c) 3
d) 4

3. In which part of the VHDL code, components must be declared?
a) Library
b) Entity
c) Architecture
d) Configuration

4. What is the property of Positional mapping?
a) Easier to write
b) Less error prone
c) Ports can be left unconnected
d) Difficult to write

5. A component has 3 ports- two inputs(a and b) and one output(y). Which of the following statement is for the positional mapping of the component?
a) LABEL : my_component PORT MAP (l, m, n);
b) LABEL : my_component PORT MAP (y, a);
c) LABEL : my_component PORT MAP (l => a, m => b, n => y);
d) LABEL : my_component PORT MAP(a, b, y>= a);

6. __________ mapping is less error prone.
a) Port
b) Positional
c) Nominal
d) Generic

7. The ports of a component can be left unconnected.
a) True
b) False

8. It is not necessary that the order of the arguments in PORT MAP is taken as the order in which ports are declared.
a) True
b) False

9. How to declare a 2 input OR gate in the structural modeling?
a)

    COMPONENT or IS
     PORT ( a, b : IN BIT;
                  x, y : OUT BIT);
    END COMPONENT;

b)

     COMPONENT or IS
     PORT ( a, b : IN BIT;
                  y : OUT BIT);
    END COMPONENT;

c)

    COMPONENT or_gate IS
     PORT ( a, b : IN BIT;
                  x,  y : OUT BIT);
    END COMPONENT;

d)

    COMPONENT or_gate IS
     PORT ( a, b : IN BIT;
                  y : OUT BIT);
    END COMPONENT;

10. Which of the following is the right way to leave a port unconnected?
a) L1 : my_component PORT MAP(a); a <= OPEN;
b) L1 : my_component PORT MAP(a := OPEN);
c) L1: my_component PORT MAP(a => OPEN);
d) L1 : my_component PORT MAP(a); a := OPEN;

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