Static Memories MCQ’s

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Static Memories”.

1. The minimum time delay between two successive memory read operations is ______
a) Cycle time
b) Latency
c) Delay
d) None of the mentioned

2. MFC is used to _________
a) Issue a read signal
b) Signal to the device that the memory read operation is complete
c) Signal the processor the memory operation is complete
d) Assign a device to perform the read operation

3. The duration between the read and the mfc signal is ______
a) Access time
b) Latency
c) Delay
d) Cycle time

4. __________ is the bottleneck, when it comes computer performance.
a) Memory access time
b) Memory cycle time
c) Delay
d) Latency

5. VLSI stands for ___________
a) Very Large Scale Integration
b) Very Large Stand-alone Integration
c) Volatile Layer System Interface
d) None of the mentioned

6. The cells in each column are connected to ______
a) Word line
b) Data line
c) Read line
d) Sense/ Write line

7. The logical addresses generated by the cpu are mapped onto physical memory by ____________
a) Relocation register
b) TLB
c) MMU
d) None of the mentioned

8. The cells in a row are connected to a common line called ______
a) Work line
b) Word line
c) Length line
d) Principle diagonal

9. The word line is driven by the _____
a) Chip select
b) Address decoder
c) Data line
d) Control line

10. A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into _____
a) 128 X 8
b) 256 X 4
c) 512 X 2
d) 1024 X 1

11. The number of external connections required in 16 X 8 memory organisation is _____
a) 14
b) 19
c) 15
d) 12

12. A 16 X 8 Organisation of memory cells, can store upto _____
a) 256 bits
b) 1024 bits
c) 512 bits
d) 128 bits

13. Circuits that can hold their state as long as power is applied is _______
a) Dynamic memory
b) Static memory
c) Register
d) Cache

14. The advantage of CMOS SRAM over the transistor one’s is _________
a) Low cost
b) High efficiency
c) High durability
d) Low power consumption

15. In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8 data lines are there.
a) 10
b) 8
c) 9
d) 12

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