Single BUS Organisation-1 MCQ’s

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Single BUS Organisation-1″.

1. A common strategy for performance is making various functional units operate parallelly.
a) True
b) False

2. The PC gets incremented _____________
a) After the instruction decoding
b) After the IR instruction gets executed
c) After the fetch cycle
d) None of the mentioned

3. The CPU is also called as ________
a) Processor hub
b) ISP
c) Controller
d) All of the mentioned

4. Which register in the processor is single directional?
a) MAR
b) MDR
c) PC
d) Temp

5. Which register is connected to the MUX?
a) Y
b) Z
c) R0
d) Temp

6. The input and output of the registers are governed by __________
a) Transistors
b) Diodes
c) Gates
d) Switches

7. The transparent register/s is/are __________
a) Y
b) Z
c) Temp
d) All of the mentioned

8. The registers, ALU and the interconnecting path together are called as ______
a) Control path
b) Flow path
c) Data path
d) None of the mentioned

9. When two or more clock cycles are used to complete data transfer it is called as ________
a) Single phase clocking
b) Multi-phase clocking
c) Edge triggered clocking
d) None of the mentioned

10. ________ signal is used to show complete of memory operation.
a) MFC
b) WMFC
c) CFC
d) None of the mentioned

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