This set of Digital Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Shift Registers”.
1. The full form of SIPO is ___________
a) Serial-in Parallel-out
b) Parallel-in Serial-out
c) Serial-in Serial-out
d) Serial-In Peripheral-Out
2. A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?
b) End around
3. Based on how binary information is entered or shifted out, shift registers are classified into _______ categories.
4. How can parallel data be taken out of a shift register simultaneously?
a) Use the Q output of the first FF
b) Use the Q output of the last FF
c) Tie all of the Q outputs together
d) Use the Q output of each FF
5. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________
6. A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains ________
7. What is meant by the parallel load of a shift register?
a) All FFs are preset with data
b) Each FF is loaded with data, one at a time
c) Parallel shifting of data
d) All FFs are set with data
8. Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
9. With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in ________
a) 4 μs
b) 40 μs
c) 400 μs
d) 40 ms
10. An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of ________
a) 16 us
b) 8 us
c) 4 us
d) 2 us