Programmable DMA Interface 8237 – 2 MCQ’s

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This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Programmable DMA Interface 8237 – 2″.

1. The register that holds the data during memory to memory data transfer is
a) mode register
b) temporary register
c) command register
d) mask register

2. The register that keeps track of all the DMA channel pending requests and status of their terminal counts is
a) mask register
b) request register
c) status register
d) count register

3. Each bit in the request register is cleared by
a) under program control
b) generation of TC
c) generation of an external EOP
d) all of the mentioned

4. The pin that clears the command, request and temporary registers, and internal first/last flipflop when it is set is
a) CLEAR
b) SET
c) HLDA
d) RESET

5. When interface 8237 does not have any valid pending DMA request then it is said to be in
a) active state
b) passive state
c) idle state
d) none of the mentioned

6. In demand transfer mode of 8237, the device stops data transfer when
a) a TC (terminal count) is reached
b) an external EOP (active low) is detected
c) the DREQ signal goes inactive
d) all of the mentioned

7. The DMA request input pin that has the highest priority is
a) DREQ0
b) DREQ1
c) DREQ2
d) DREQ3

8. To complete a DMA transfer, a memory to memory transfer requires
a) a read from memory cycle
b) a write to memory cycle
c) a read-from and write-to memory cycle
d) none of the mentioned

9. The mode of 8237 in which the device transfers only one byte per request is
a) block transfer mode
b) single transfer mode
c) demand transfer mode
d) cascade mode

10. Which of the following command is used to make all the internal registers of 8237 clear?
a) clear first/last flipflop
b) master clear command
c) clear mask register
d) none of the mentioned

11. The transfer of a block of data from one set of memory address to another takes place in
a) block transfer mode
b) demand transfer mode
c) memory to memory transfer mode
d) cascade mode

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