Large Memories MCQ’s

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Large Memories”.

1. To organise large memory chips we make use of ______
a) Integrated chips
b) Upgraded hardware
c) Memory modules
d) None of the mentioned

2. The less space consideration as lead to the development of ________ (for large memories).
a) SIMM’s
b) DIMS’s
c) SRAM’s
d) Both SIMM’s and DIMS’s

3. The chip can be disabled or cut off from an external connection using ______
a) Chip select
b) LOCK
c) ACPT
d) RESET

4. The SRAM’s are basically used as ______
a) Registers
b) Caches
c) TLB
d) Buffer

5. The address lines multiplexing is done using ______
a) MMU
b) Memory controller unit
c) Page table
d) Overlay generator

6. The RAS and CAS signals are provided by the ______
a) Mode register
b) CS
c) Memory controller
d) None of the mentioned

7. The higher order bits of the address are used to _____
a) Specify the row address
b) Specify the column address
c) Input the CS
d) None of the mentioned

8. The controller multiplexes the addresses after getting the _____ signal.
a) INTR
b) ACK
c) RESET
d) Request

9. Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then the refresh overhead of the chip is ______
a) 0.0021
b) 0.0038
c) 0.0064
d) 0.0128

10. When DRAM’s are used to build a complex large memory, then the controller only provides the refresh counter.
a) True
b) False

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