Interconnection Topologies MCQ’s

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This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Interconnection Topologies”.

1. In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data or instructions is
a) one processor
b) two processors
c) more than two processors
d) none of the mentioned

2. In multiport memory configuration, the processor(s) that address the multiport memory is(are)
a) 1
b) 2
c) 3
d) many

3. The memory of a microprocessor serves as
a) storage of individual instructions
b) temporary storage for the data
c) storing common instructions or data for all processors
d) all of the mentioned

4. The memory space of a processor that is mapped to other processor/processors and vice-versa is known as
a) multi microprocessor system
b) memory technique
c) bus window technique
d) mapping technique

5. Bus switches are present in
a) bus window technique
b) crossbar switching
c) linked input/output
d) shared bus

6. The configuration, in which all the processing elements are connected to a central switching element, that may be independent processor via dedicated paths is
a) star
b) loop
c) complete
d) irregular

7. The disadvantage of the bus window technique is
a) both processors must know about bus window
b) both processors must know the address map
c) loss of effective local memory space
d) all of the mentioned

8. Which of the following is not a type of configuration that is based on physical interconnections between the processors?
a) star configuration
b) loop configuration
c) regular topologies
d) incomplete interconnection

9. The configuration that is not suitable for a large number of processors is
a) star
b) loop
c) complete
d) regular

10. The array processor architecture is an example of
a) star
b) loop
c) complete
d) regular

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