Functions and Subprograms – 3 MCQ’s

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This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Functions and Subprograms – 3″.

1. Apart from using WAIT statements, which of the following is not possible in functions?
a) Variable assignment
b) Return statement
c) Variable declaration
d) Signal assignment

2. Conversion functions are used to _________
a) Resolve value of a signal with multiple drivers
b) Convert one data type into another
c) Convert one data object into another
d) Resolve value of a constant with multiple drivers

3. The variables declared inside a function retain their values between two function calls.
a) True
b) False

4. In VHDL it is not possible to use recursive functions.
a) True
b) False

5. Which of the following is not the legal name of a function?
a) abc
b) +
c) then
d) my_func

6. The minimum number of parameters that must be there in a function is ___________
a) 0
b) 1
c) 2
d) 3

7. In the following code, which of the lines corresponds to the function call and function definition?

L1 : ARCHITECTURE adder OF adder IS
L2 : BEGIN
L3 : x <= sum ( SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC);
L4 : END adder;
L5 : FUNCTION sum ( SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC) RETURN STD_LOGIC IS
L6 : VARIABLE c : INTEGER;
L7 : BEGIN
L8 : c<= a OR b;
L9 : RETURN c;
L10 : END sum;

a) L5, L3
b) L5, L9
c) L3, L7
d) L3, L5

8. If a function has an operator sign as its name, then what will be the purpose of that function?
a) Conversion
b) Overloading
c) Resolution
d) Define the data type

9. What is the alternative for specifying the vector size in the function?
a) Not using arrays
b) Defining every single element differently
c) Defining a subtype
d) Using bit vector

10. What is the ease provided by using functions?
a) Easy debugging
b) Easy reading
c) Easy calling
d) Easy implementation

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