DMA Transfers and Operations MCQ’s

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This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “DMA Transfers and Operations”.

1. The bus is available when the DMA controller receives the signal
a) HRQ
b) HLDA
c) DACK
d) All of the mentioned

2. To indicate the I/O device that its request for the DMA transfer has been honored by the CPU, the DMA controller pulls
a) HLDA signal
b) HRQ signal
c) DACK (active low)
d) DACK (active high)

3. The 8257 is able to accomplish the operation of
a) verifying DMA operation
b) write operation
c) read operation
d) all of the mentioned

4. If more than one channel requests service simultaneously, the transfer will occur as
a) multi transfer
b) simultaneous transfer
c) burst transfer
d) none of the mentioned

5. The number of clock cycles required for an 8257 to complete a transfer is
a) 2
b) 4
c) 8
d) none of the mentioned

6. The priority of the channels varies frequently in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned

7. The continuous transfer may be interrupted by an external device by pulling down the signal
a) HRQ
b) DACK (active low)
c) DACK (active high)
d) HLDA

8. In 8257, if each device connected to a channel is assigned to a fixed priority then it is said to be in
a) rotating priority scheme
b) fixed priority scheme
c) rotating priority and fixed priority scheme
d) none of the mentioned

9. The register of 8257 that can only be written in is
a) DMA address register
b) Terminal count register
c) Mode set register
d) Status register

10. The operation that can be performed on the status register is
a) write operation
b) read operation
c) read and write operations
d) none of the mentioned

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