Common Terms used in VHDL MCQ’s

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This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Common Terms used in VHDL”.

1. A package in VHDL consists of _________
a) Commonly used architectures
b) Commonly used tools
c) Commonly used data types and subroutines
d) Commonly used syntax and variables

2. Complete description of the circuit to be designed is given in _________
a) Architecture
b) Entity
c) Library
d) Configurations

3. An entity can have more than one architecture.
a) True
b) False

4. Which of the following is the basic building block of a design?
a) Architecture
b) Entity
c) Process
d) Package

5. In VHDL, Bus is a type of ________
a) Signal
b) Constant
c) Variable
d) Driver

6. What is the use of the Configuration statement?
a) To configure the components exactly in design
b) To complete the design process by adding libraries
c) To add more than one entities into a single architecture
d) To add some component in any entity architecture pair

7. Driver can be seen as a _______ of the signal.
a) Part
b) Type
c) Final value
d) Source

8. What is the use of Generics in VHDL?
a) To turn on and off the drivers
b) To pass information to the entity
c) To describe architecture
d) To divide code into small processes

9. Predefined data for an VHDL object is called ________
a) Generic
b) Constant
c) Attribute
d) Library

10. Which of the following describes the structure of VHDL code correctly?
a) Library Declaration; Entity Declaration; Architecture Declaration; Configurations
b) Entity Declaration; Configuration; Library Declaration; Architecture Declaration
c) Configuration; Library Declaration; Entity Declaration; Architecture Declaration
d) Library Declaration; Configuration; Entity Declaration; Architecture Declaration

11. A process is the basic unit of execution in VHDL.
a) True
b) False

12. Which of the following statement is true?
a) Package is a collection of Libraries
b) Library is a collection of Packages
c) Entity is a collection of Packages
d) Architecture is a collection of Entities

13. Which of the following is correctly declared library for VHDL code?
a)

LIBRARY library_name;
USE package_name.parts;

b)

LIBRARY package_name.parts;
LIBRARY library_name;

c)

USE library_name;
LIBRARY library_name.package_name.parts

d)

LIBRARY library_name;
USE library_name.package_name.parts

14. Which of the following is used at the end of a statement?
a) ; (Semicolon)
b) — ( double hyphen)
c) _ (underscore)
d) No sign is used at the end of statement

15. One can’t use more than one library in the VHDL code.
a) True
b) False

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