Cache Miss and Hit MCQ’s

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This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Cache Miss and Hit”.

1. When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False

2. In memory interleaving, the lower order bits of the address is used to _____________
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
d) None of the mentioned

3. The main memory is structured into modules each with its own address register called ______
a) ABR
b) TLB
c) PC
d) IR

4. The number successful accesses to memory stated as a fraction is called as _____
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate

5. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit

6. If hit rates are well below 0.9, then they’re called as speedy computers.
a) True
b) False

7. The number failed attempts to access memory, stated in the form of a fraction is called as _________
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate

8. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of ______
a) Hit
b) Miss
c) Delay
d) None of the mentioned

9. The extra time needed to bring the data into memory in case of a miss is called as __________
a) Delay
b) Propagation time
c) Miss penalty
d) None of the mentioned

10. The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.
a) True
b) False

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