Biasing of JFET and MOSFET MCQ’s

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This set of Analog Electronic Circuits Multiple Choice Questions & Answers (MCQs) focuses on “Biasing of JFET and MOSFET”.

1. In the given situation for n-channel JFET, we get drain-to-source current is 5mA. What is the current when VGS = – 6V?

a) 5 mA
b) 0.5A
c) 0.125 A
d) 0.5A

2. Consider the following circuit. Given that VDD = 15V, VP = 2V, and IDS = 3mA, to bias the circuit properly, select the proper statement.

a) RD < 6kΩ
b) RD > 6kΩ
c) RD > 4kΩ
d) RD < 4kΩ

3. Which of the following statements are true?

P: JFET is biased to operate it in active region
Q: MOSFET is biased to operate it in saturation region

a) Both P and Q are correct
b) P is correct and Q is incorrect
c) P is incorrect and Q is correct
d) Both P and Q are incorrect

4. Consider the circuit shown. VDS=3 V. If IDS=2mA, find VDD to bias circuit.

a) -30V
b) 30V
c) 33V
d) Any value of voltage less than 12 V

5. Consider the following circuit. Process transconductance parameter = 0.50 mA/V2, W/L=1, Threshold voltage = 3V, VDD = 20V. Find the operating point of circuit.

a) 20V, 25mA
b) 13V, 22mA
c) 12.72V, 23.61mA
d) 20V, 23.61mA

6. To bias a e-MOSFET ___________
a) we can use either gate bias or a voltage divider bias circuit
b) we can use either gate bias or a self bias circuit
c) we can use either self bias or a voltage divider bias circuit
d) we can use any type of bias circuit

7. Given VDD = 25V, VP = -3V. When VGS = -3V, IDS = 10mA. Find the operating point of the circuit.

a) -3.83V, 0.766mA
b) -2.345V, 0.469mA
c) 3.83V, 0.469mA
d) 2.3V, 0.7mA

8. For a MOSFET, the pinch-off voltage is -3V. Gate to source voltage is 20V. W/L ratio is 5. Process transconductance parameter is 40μA/V2. Find drain to source current in saturation.
a) 0.10 mA
b) 0.05mA
c) – 0.05mA
d) – 50A

9. Consider the following circuit. IDSS = 2mA, VDD = 30V. Find R, given that VP = – 2V.

a) 10kΩ
b) 4kΩ
c) 2kΩ
d) 5kΩ

10. Which of the following statements are true?

A: In a self bias circuit, the current IDS is not stable.
B: Source capacitance, CS, parallel to RS, reduces stability.

a) Both statements are correct and B is the correct reasoning
b) Both statements are correct but B is not the correct reason for it
c) Statement A is correct while statement B is wrong
d) Both statements are incorrect

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