This set of VHDL Multiple Choice Questions & Answers (MCQs) focuses on “Behavioural Modelling”.
1. For any concurrent assignment statement, which of the following is true?
a) The statement is executed once
b) The statement is executed twice
c) The value of left operand is assigned to right operand
d) The statement is executed as many times as the value changes
2. a < = b after 10ns; In this statement the keyword ‘after’ is used for introducing delay.
3. The most basic form of behavioral modeling in VHDL is _______
a) IF statements
b) Assignment statements
c) Loop statements
d) WAIT statements
4. Which of the circuit is described by following VHDL code?
LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY my_func IS PORT(x, a, b : IN std_logic; q : OUT std_logic); END my_func; ARCHITECTURE behavior OF my_func IS SIGNAL s : INTEGER; BEGIN WITH s SELECT q <= a AFTER 10 ns WHEN 0; b AFTER 10 ns WHEN 1; s <= 0 WHEN x = ‘0’ ELSE 1 WHEN x = ‘1’; END behavior;
5. What is the use of simulation deltas in VHDL code?
a) To create delays in simulation
b) To assign values to signals
c) To order some events
d) Evaluate assignment statements
6. The main problem with behavioral modeling is ________
a) Asynchronous delays
c) No delay
d) Supports single driver only
7. VHDL can’t handle multiply driven signals.
8. Refer to the VHDL code given below, which of the following signal is driven by multiple drivers?
LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY function IS PORT (b, c : IN BIT; a, d : OUT BIT); END function; ARCHITECTURE behavior OF my_func IS BEGIN a <= b; a <= c; d <= b; END behavior;
9. Which function is used to create a single value for multiple driver signals?
a) Resolution function
c) Concurrent assignments
d) Sequential assignments
10. A signal is driven by two signals b and c. How the value of b and c will be resolved to calculate the value of a?
a) By short circuiting both driver
b) By open circuiting one driver
c) By AND operation between two drivers
d) By NOT operation of both drivers